Stacking field-effect transistors (FETs) in the vertical direction gives an additional dimension for complementary metal-oxide-semiconductor (CMOS) area scaling. However, it is very challenging to stack planar FETs.
Vertical field effect transistors (VFETs) however have a unique structure that can help the stacking process. Namely, as opposed to planar CMOS devices, VFETs are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel.
Logic gate designs (e.g., NAND, NOR, Inverter) in the scheme of direct stacking would be desirable.